Three-dimensional semiconductor memory device

ABSTRACT

A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C §119 to Korean Patent Application No. 10-2019-0033056 filed on Mar. 22,2019 in the Korean Intellectual Property Office, the entire contents ofwhich are hereby incorporated by reference.

BACKGROUND

Inventive concepts relate to a semiconductor device, and, moreparticularly, to three-dimensional semiconductor memory devices withimproved reliability.

Semiconductor devices have been highly integrated for providing highperformance and lower prices, which are desired by customers. Becauseintegration of semiconductor devices is a factor in determining productprice, demand for highly integrated semiconductor devices may increase.Integration of typical two-dimensional or planar semiconductor devicesis primarily determined by the area occupied by a unit memory cell, suchthat it is influenced by the level of technology for forming finepatterns. However, the processing equipment used to increase patternfineness may set a practical limitation on increasing the integration ofthe two-dimensional or planar semiconductor devices due to the costthereof. Therefore, there have been proposed three-dimensionalsemiconductor memory devices having three-dimensionally arranged memorycells.

SUMMARY

Some example embodiments of the inventive concepts provide athree-dimensional semiconductor memory device with improved reliability.

According to some example embodiments of the present inventive concepts,a semiconductor memory device may comprise: a stack structure comprisinga plurality of electrodes and a plurality of insulating layers that arealternately stacked on a substrate; and a vertical channel structurepenetrating the stack structure. The vertical channel structure maycomprise a semiconductor pattern and a vertical insulating layer betweenthe semiconductor pattern and the plurality of electrodes. The verticalinsulating layer may comprise a charge storage layer, a fillinginsulating layer, and a tunnel insulating layer. The vertical insulatinglayer may have a cell region between the semiconductor pattern and eachof the plurality of electrodes and a cell separation region between thesemiconductor pattern and each of the plurality of insulating layers.The charge storage layer may comprise a first portion and a remainingportion in the cell region, The first portion of the charge storagelayer of the cell region may be in physical contact with the tunnelinsulating layer. The filling insulating layer may be between thesemiconductor pattern and the remaining portion of the charge storagelayer of the cell region.

According to some example embodiments of the present inventive concepts,a semiconductor memory device may comprise: a stack structure comprisinga plurality of electrodes and a plurality of insulating layers that arealternately stacked on a substrate; and a vertical channel structurepenetrating the stack structure. The vertical channel structure maycomprise a semiconductor pattern and a vertical insulating layer betweenthe semiconductor pattern and the plurality of electrodes. The verticalinsulating layer may comprise a charge storage layer, a fillinginsulating layer, and a tunnel insulating layer. The filling insulatinglayer and the tunnel insulating layer may be between the charge storagelayer and the semiconductor pattern. The vertical insulating layer mayhave a cell region between the semiconductor pattern and each of theplurality of electrodes and a cell separation region between thesemiconductor pattern and each of the plurality of insulating layers.The filling insulating layer of the cell region may have a firstthickness in a first direction parallel to the substrate. The fillinginsulating layer of the cell separation region may have a secondthickness in the first direction. The second thickness may be greaterthan the first thickness.

According to some example embodiments of the present inventive concepts,a semiconductor memory device may comprise: a stack structure comprisinga plurality of electrodes and a plurality of insulating layers that arealternately stacked on a substrate; and a vertical channel structurepenetrating the stack structure. The vertical channel structure maycomprise a semiconductor pattern and a vertical insulating layer betweenthe semiconductor pattern and the plurality of electrodes. The verticalinsulating layer may include a charge storage layer, a fillinginsulating layer, and a tunnel insulating layer. The vertical insulatinglayer may have a cell region between the semiconductor pattern and eachof the plurality of electrodes and a cell separation region between thesemiconductor pattern and each of the plurality of insulating layers. Abottom surface of the cell separation region may be at a levelsubstantially the same as a level of a bottom surface of the insulatinglayer adjacent to the cell separation region. A top surface of the cellseparation region may be at a level substantially the same as a level ofa top surface of the insulating layer adjacent to the cell separationregion. The filling insulating layer may extend from the bottom surfaceof the cell separation region toward the top surface of the cellseparation region.

According to some example embodiments of the present inventive concepts,a semiconductor memory device may comprise: a stack structure comprisinga plurality of electrodes and a plurality of insulating layers that arealternately stacked on a substrate; and a vertical channel structurepenetrating the stack structure. The vertical channel structure maycomprise a semiconductor pattern and a charge storage layer between thesemiconductor pattern and the plurality of electrodes. Each of theplurality of electrodes may comprise a body part and a protrusion partthat protrudes from the body part toward the semiconductor pattern. Aboundary between the body part and the protrusion part may be alignedwith an outer sidewall of the charge storage layer. The outer sidewallmay face the plurality of insulating layers. The body part may have afirst thickness. The protrusion part may have a second thickness thatdecreases with decreasing distance from the semiconductor pattern. Amaximum value of the second thickness of the protrusion part may be thesame as or less than the first thickness.

According to some example embodiments of the present inventive concepts,a semiconductor memory device may comprise: a stack structure comprisinga plurality of electrodes and a plurality of insulating layers that arealternately stacked on a substrate; and a vertical channel structurepenetrating the stack structure. The vertical channel structure maycomprise a semiconductor pattern and a vertical insulating layer betweenthe semiconductor pattern and the plurality of electrodes. The verticalinsulating layer may comprise a charge storage layer and a tunnelinsulating layer between the charge storage layer and the semiconductorpattern. The vertical insulating layer may have a data storage partbetween the semiconductor pattern and each of the plurality ofelectrodes and a connection part between a pair of the data storageparts adjacent to each other in a direction normal to the substrate. Theconnection part may include a filling insulating layer between thetunnel insulating layer and the charge storage layer. The fillinginsulating layer may be in physical contact with the tunnel insulatinglayer. The filling insulating layer may separate the tunnel insulatinglayer of the connection part from the charge storage layer of theconnection part.

According to some example embodiments of the present inventive concepts,a semiconductor memory device may comprise: a stack structure comprisinga plurality of electrodes and a plurality of insulating layers that arealternately stacked on a substrate; and a vertical channel structurepenetrating the stack structure. The vertical channel structure maycomprise a semiconductor pattern and a vertical insulating layer betweenthe semiconductor pattern and the plurality of electrodes. The verticalinsulating layer may include a charge storage layer. The verticalinsulating layer may have a data storage part between the semiconductorpattern and each of the plurality of electrodes and a connection partbetween a pair of the data storage parts adjacent to each other in adirection normal to the substrate. The connection part may include anair gap and a filling insulating layer that are between thesemiconductor pattern and each of the plurality of insulating layers.

According to some example embodiments of the present inventive concepts,a semiconductor memory device comprises a stack structure comprises aplurality of electrodes and a plurality of insulating layers that arealternately stacked on a substrate and a vertical channel structurepenetrating the stack structure. The vertical channel structurecomprises a semiconductor pattern and a vertical insulating layerbetween the semiconductor pattern and the plurality of electrodes. Thevertical insulating layer comprises a charge storage layer and a tunnelinsulating layer between the charge storage layer and the semiconductorpattern. The vertical insulating layer has a data storage part betweenthe semiconductor pattern and each of the plurality of electrodes and aconnection part between a pair of the data storage parts adjacent toeach other in a direction normal to the substrate. A length of thecharge storage layer of the connection part is greater than a distancebetween the pair of the data storage parts.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic diagram showing a simplifiedconfiguration of a three-dimensional semiconductor memory deviceaccording to some example embodiments of the inventive concepts.

FIG. 2 illustrates a simplified block diagram showing a cell array of athree-dimensional semiconductor memory device according to some exampleembodiments of inventive concepts.

FIG. 3 illustrates a plan view showing a three-dimensional semiconductormemory device according to some example embodiments of the inventiveconcepts.

FIG. 4 illustrates a cross-sectional view taken along line I-I′ of FIG.3.

FIG. 5A illustrates an enlarged cross-sectional view showing section Mof FIG. 4.

FIG. 5B illustrates a simplified perspective view showing section M ofFIG. 4.

FIGS. 6 to 11 illustrate cross-sectional views taken along line I-I′ ofFIG. 3 showing a method of fabricating a three-dimensional semiconductormemory device according to some example embodiments of the inventiveconcepts.

FIGS. 12A and 12B illustrate enlarged cross-sectional views showingsection M of FIG. 8.

FIGS. 13A, 13B, and 13C illustrate enlarged cross-sectional viewsshowing section M of FIG. 9.

FIG. 14 illustrates an enlarged cross-sectional view showing section Mof FIG. 11.

FIGS. 15 to 22 illustrate enlarged cross-sectional views of section Mdepicted in FIG. 4 showing a three-dimensional semiconductor memorydevice according to some example embodiments of the inventive concepts.

FIG. 23 illustrates an enlarged cross-sectional view of section Ndepicted in FIG. 4, showing a three-dimensional semiconductor memorydevice according to some example embodiments of the inventive concepts.

DETAILED DESCRIPTION OF EMBODIMENTS

The inventive concepts will now be described more fully with referenceto the accompanying drawings, in which example embodiments of theinventive concept are shown. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed items.It will be understood that when an element is referred to as being “on”,“attached” to, “connected” to, “coupled” with, “contacting”, etc.,another element, it can be directly on, attached to, connected to,coupled with or contacting the other element or intervening elements mayalso be present. In contrast, when an element is referred to as being,for example, “directly on”, “directly attached” to, “directly connected”to, “directly coupled” with or “directly contacting” another element,there are no intervening elements present. It is noted that aspectsdescribed with respect to one embodiment may be incorporated indifferent embodiments although not specifically described relativethereto. That is, all embodiments and/or features of any embodiments canbe combined in any way and/or combination.

FIG. 1 illustrates a schematic diagram showing a simplifiedconfiguration of a three-dimensional semiconductor memory deviceaccording to some example embodiments of the inventive concepts.

Referring to FIG. 1, a three-dimensional semiconductor memory device mayinclude a cell array region CAR and a peripheral circuit region. Theperipheral circuit region may include row decoder regions ROW DCR, apage buffer region PBR, a column decoder region COL DCR, and a controlcircuit region (not shown). In some embodiments, a connection region CTRmay be disposed between the cell array region CAR and the row decoderregions ROW DCR.

The cell array region CAR may include a memory cell array including aplurality of memory cells. In some embodiments, the memory cell arraymay include three-dimensionally arranged memory cells and a plurality ofword lines and bit lines electrically connected to the memory cells.

The row decoder region ROW DCR may include a row decoder that selectsthe word lines of the memory cell array, and the connection region CTRmay include a wiring structure that electrically connects the memorycell array and the row decoder to each other. Based on addressinformation, the row decoder may select one of the word lines of thememory cell array. The row decoder may provide word line voltages to theselected word line and unselected word lines in response to a controlsignal from a control circuit.

The page buffer region PBR may include a page buffer that reads datastored in the memory cells. Depending on an operating mode, the pagebuffer may temporarily store data to be stored in the memory cells orsense data stored in the memory cells. The page buffer may act as awrite driver circuit in a program operating mode and as a senseamplifier circuit in a read operating mode.

The column decoder region COL DCR may include a column decoder connectedto the bit lines of the memory cell array. The column decoder mayprovide a data transmission path between the page buffer and an externaldevice (e.g., a memory controller).

FIG. 2 illustrates a simplified block diagram showing a cell array of athree-dimensional semiconductor memory device according to some exampleembodiments of the inventive concepts.

Referring to FIG. 2, the cell array region CAR may include a pluralityof cell array blocks BLK1, BLK2, . . . , and BLKn. Each of the cellarray blocks BLK1, BLK2, . . . , and BLKn may include a stack structurehaving electrodes stacked along a third direction D3 on a planeelongated along first and second directions D1 and D2. The stackstructure may combine with a plurality of vertical structures (orsemiconductor pillars) to constitute three-dimensionally arranged memorycells. In addition, each of the cell array blocks BLK1, BLK2, . . . ,and BLKn may include bit lines electrically connected to the memorycells.

FIG. 3 illustrates a plan view showing a three-dimensional semiconductormemory device according to some example embodiments of the inventiveconcepts. FIG. 4 illustrates a cross-sectional view taken along lineI-I′ of FIG. 3. FIG. 5A illustrates an enlarged cross-sectional viewshowing section M of FIG. 4. FIG. 5B illustrates a simplifiedperspective view showing section M of FIG. 4.

Referring to FIGS. 3, 4, 5A, and 5B, a substrate 100 may include a cellarray region CAR. For example, the substrate 100 may be a siliconsubstrate, a germanium substrate, or a silicon-germanium substrate. Thesubstrate 100 may have a first conductivity type (e.g., p-type).

A cell array block BLK may be disposed on the substrate 100. The cellarray block BLK may include a stack structure ST having first insulatinglayers IL1 and electrodes EL that are vertically and alternatelystacked. The stack structure ST may extend along a second direction D2on the cell array region CAR. FIG. 3 illustrates an example of a singlestack structure ST, but the inventive concepts are not limited thereto.For example, the stack structure ST may be provided in plural. Theplurality of stack structures ST may be arranged along a first directionD1 intersecting the second direction D2.

Common source regions CSR may be provided on opposite sides of the stackstructure ST. The common source regions CSR may be formed on an upperportion of the substrate 100. The common source regions CSR may extendparallel to the stack structure ST along the second direction D2. Thecommon source regions CSR may be doped with impurities to have a secondconductivity type. For example, the common source regions CSR may bedoped with n-type impurities, such as arsenic (As) or phosphorous (P).

A common source plug CSP may be coupled to the common source region CSR.The common source plug CSP may vertically overlap the common sourceregion CSR. The common source plug CSP may extend parallel to the stackstructure ST along the second direction D2. An insulating spacer SP maybe interposed between the common source plug CSP and the stack structureST.

The electrodes EL of the stack structure ST may be stacked along a thirddirection D3 perpendicular to a top surface of the substrate 100. Theelectrodes EL vertically overlapping each other may be verticallyseparated from each other across the first insulating layer IL1 disposedtherebetween.

A lowermost electrode EL of the stack structure ST may be a lowerselection line. An uppermost electrode EL of the stack structure ST maybe an upper selection line. The electrodes EL other than the lower andupper selection lines may be word lines. A separation insulating patternSEP may extend in the second direction D2, while running across theuppermost electrode EL (or the upper selection line). The separationinsulating pattern SEP may include an insulating material (e.g., asilicon oxide layer).

The stack structure ST may further include a second insulating layer IL2on the uppermost electrode EL (or the upper selection line). The secondinsulating layer IL2 may be thicker than the first insulating layer IL1.The second insulating layer IL2 may at least partially cover a topsurface of the separation insulating pattern SEP.

The electrodes EL may include a conductive material selected from thegroup consisting of doped semiconductors (e.g., doped silicon), metals(e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g.,titanium nitride or tantalum nitride), and transition metals (e.g.,titanium or tantalum). The first insulating layers IL1 and the secondinsulating layer IL2 may include a silicon oxide layer.

The cell array region CAR may be provided thereon with a plurality ofvertical channel structures VS penetrating the stack structure ST. Thevertical channel structures VS may be provided in corresponding channelholes CH of the stack structure ST. For example, a first column maycomprise four vertical channel structures VS arranged in the firstdirection D1, and a second column may comprise five vertical channelstructures VS arranged in the first direction D1. The first column andthe second column may be arrayed repeatedly and alternately along thesecond direction D2.

Each of the vertical channel structures VS may include a verticalinsulating layer VP, an upper semiconductor pattern USP, a lowersemiconductor pattern LSP, and a buried insulating pattern VI. Thevertical insulating layer VP may extend along an inner wall of thechannel hole CH toward the substrate 100. The upper semiconductorpattern USP may at least partially cover an inner wall of the verticalinsulating layer VP and extend together with the vertical insulatinglayer VP toward the substrate 100.

The lower semiconductor pattern LSP may be provided in a lower portionof the channel hole CH and in physical contact with the substrate 100.The lower semiconductor pattern LSP may penetrate the lowermostelectrode EL (or the lower selection line) of the stack structure ST. Anoxidation pattern OP may be interposed between the lower semiconductorpattern LSP and the lowermost electrode EL (or the lower selectionline).

The upper semiconductor pattern USP may have a pipe shape whose bottomis closed. The upper semiconductor pattern USP may have a bottom surfacein direct physical contact with the lower semiconductor pattern LSP. Theupper semiconductor pattern USP may have an inside at least partiallyfilled with the buried insulating pattern VI. Each of the uppersemiconductor pattern USP and the buried insulating pattern VI may havea diameter that gradually decreases with decreasing distance from thesubstrate 100. In some embodiments, the diameter may decreasemonotonically with decreasing distance from the substrate 100. The lowerand upper semiconductor patterns LSP and USP may be used as a channel ofa three-dimensional semiconductor memory device according to someexample embodiments of the inventive concepts.

For example, the lower and upper semiconductor patterns LSP and USP mayinclude silicon (Si), germanium (Ge), or a combination thereof, and havedifferent crystal structures from each other. The lower and uppersemiconductor patterns LSP and USP may have one or more materialsselected from a single crystalline structure, an amorphous structure,and a polycrystalline structure. The lower and upper semiconductorpatterns LSP and USP may be either undoped or doped with impurities tohave the first conductivity type, which is the same as that of thesubstrate 100.

In other embodiments, the lower semiconductor pattern LSP may beomitted. The upper semiconductor pattern USP may extend toward anddirectly physically contact the substrate 100. For example, arelationship between the vertical channel structure VS and the substrate100 is not limited to that shown in FIG. 4, but may vary in accordancewith different embodiments of the inventive concepts.

A conductive pad PA may be provided on an upper portion of each of thevertical channel structures VS. The conductive pad PA may at leastpartially cover a top surface of each of the vertical insulating layerVP, the upper semiconductor pattern USP, and the buried insulatingpattern VI. The conductive pad PA may include an impurity-dopedsemiconductor material and/or a conductive material. The conductive padPA may have a top surface generally coplanar with that of the secondinsulating layer IL2. The conductive pad PA may electrically connect theupper semiconductor pattern USP to a bit line contact plug BPLG, whichwill be described below.

The stack structure ST may be provided thereon with a third insulatinglayer IL3 and a fourth insulating layer IL4 that are sequentiallystacked. The fourth insulating layer IL4 may be provided thereon withbit lines BL extending in the first direction D1. The bit line BL andthe conductive pads PA may be provided therebetween with bit linecontact plugs BPLG penetrating the fourth and third insulating layersIL4 and IL3. The bit line BL may be electrically connected through thebit line contact plug BPLG to the vertical channel structure VS.

Returning to FIGS. 5A and 5B, each of the electrodes EL may include anelectrode pattern GM, a barrier pattern BM, and a dielectric pattern GI.The barrier pattern BM may be interposed between the electrode patternGM and the dielectric pattern GI. The electrode pattern GM may include aconductive material selected from the group consisting of dopedsemiconductors, metals, and transition metals. The barrier pattern BMmay include conductive metal nitride. The dielectric pattern GI mayinclude one or more of a silicon oxide layer, a silicon nitride layer, asilicon oxynitride layer, and/or a high-k dielectric material. Forexample, the high-k dielectric material may include hafnium oxide,hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconiumsilicon oxide, tantalum oxide, titanium oxide, barium strontium titaniumoxide, barium titanium oxide, strontium titanium oxide, lithium oxide,aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or acombination thereof.

The vertical insulating layer VP may include a blocking insulating layerBK, a charge storage layer TL, a filling insulating layer FM, and atunnel insulating layer TN that are interposed between the electrode ELand the upper semiconductor pattern USP. For example, the blockinginsulating layer BK may be provided on the electrode EL and the firstinsulating layer IL1. The blocking insulating layer BK may at leastpartially cover the electrode EL and the first insulating layer IL1. Thecharge storage layer TL may be provided on the blocking insulating layerBK. The tunnel insulating layer TN may be provided on the charge storagelayer TL. The filling insulating layer FM may at least partially fill aspace between the charge storage layer TL and the tunnel insulatinglayer TN. The tunnel insulating layer TN may at least partially cover anouter sidewall of the upper semiconductor pattern USP.

For example, the blocking insulating layer BK may include a siliconoxide layer. The charge storage layer TL may include a silicon nitridelayer, a silicon oxynitride layer, and/or a silicon-rich nitride layer.The filling insulating layer FM may include a silicon oxide layer, asilicon nitride layer, and/or a silicon oxynitride layer. The tunnelinsulating layer TN may include a material whose energy bandgap isgreater than that of the charge storage layer TL. The tunnel insulatinglayer TN may include a silicon oxide layer and/or a high-k insulatinglayer, such as an aluminum oxide layer and/or a hafnium oxide layer.

The vertical insulating layer VP may include a cell region CR betweenthe electrode EL and the upper semiconductor pattern USP and alsoinclude a cell separation region SCR between the first insulating layerIL1 and the upper semiconductor pattern USP.

The cell region CR may be located at the same vertical level relative tothe substrate 100 as that of the electrode EL. For example, the cellregion CR may have a bottom surface at substantially the same level asthat of a bottom surface of the electrode EL, and also have a topsurface at substantially the same level as that of a top surface of theelectrode EL.

The cell separation region SCR may be located at the same vertical levelas that of the first insulating layer IL1. For example, the cellseparation region SCR may have a bottom surface at substantially thesame level as that of a bottom surface of the first insulating layerIL1, and also have a top surface at substantially the same level as thatof a top surface of the first insulating layer IL1.

The vertical insulating layer VP may include a plurality of cell regionsCR between corresponding electrodes EL and the upper semiconductorpattern USP. The vertical insulating layer VP may include a plurality ofcell separation regions SCR between corresponding first insulatinglayers IL1 and the upper semiconductor pattern USP. The cell separationregion SCR may be interposed between a pair of cell regions CRvertically adjacent to each other. For example, the cell separationregion SCR may connect the pair of cell regions CR to each other.

A portion of the charge storage layer TL of the cell region CR maydirectly physically contact the tunnel insulating layer TN. A remainingportion of the charge storage layer TL of the cell region CR may bespaced apart from the tunnel insulating layer TN across the fillinginsulating layer FM. For example, the filling insulating layer FM may beinterposed between the upper semiconductor pattern USP and the remainingportion of the charge storage layer TL.

The filling insulating layer FM of the cell separation region SCR may beinterposed between the charge storage layer TL and the uppersemiconductor pattern USP. The filling insulating layer FM of the cellseparation region SCR may be interposed between the charge storage layerTL and the tunnel insulating layer TN. The filling insulating layer FMof the cell separation region SCR may extend from the bottom surface ofthe cell separation region SCR to the top surface of the cell separationregion SCR. The filling insulating layer FM of the cell separationregion SCR may extend from the cell region CR above the cell separationregion SCR to the cell region CR below the cell separation region SCR.

The filling insulating layer FM of the cell region CR may have a fourththickness T4 horizontally as shown in FIG. 5A. For example, the fillinginsulating layer FM of the cell region CR may have a fourth thickness T4in the first direction D1. The fourth thickness T4 of the fillinginsulating layer FM may increase with decreasing distance from the cellseparation region SCR. In some embodiments, the fourth thickness T4 mayincrease monotonically with decreasing distance from the cell separationregion SCR. The filling insulating layer FM of the cell separationregion SCR may have a fifth thickness T5 horizontally as shown in FIG.5A. The fifth thickness T5 may be greater than the fourth thickness T4.

The electrode EL may include a body part BP and a protrusion part PP.The charge storage layer TL of the cell separation region SCR may havean outer sidewall OSW facing the first insulating layer IL1. The bodypart BP of the electrode EL may be a distal end of the electrode EL,which distal end protrudes more toward the upper semiconductor patternUSP than the outer sidewall OSW of the charge storage layer TL. Theouter sidewall OSW of the charge storage layer TL may define a boundarybetween the body part BP and the protrusion part PP. For example, theboundary between the body part BP and the protrusion part PP may bevertically aligned with the outer sidewall OSW of the charge storagelayer TL.

The body part BP may have a top surface at least partially covered bythe first insulating layer IL1 above the body part BP. The body part BPmay have a bottom surface at least partially covered with the firstinsulating layer IL1 below the body part BP. The protrusion part PP mayextend from the body part BP toward the upper semiconductor pattern USP.

The body part BP may have a first thickness T1. The first thickness T1may be substantially the same as a distance between the first insulatinglayers IL1 vertically adjacent to each other. The protrusion part PP mayhave a second thickness T2. The second thickness T2 of the protrusionpart PP may gradually decrease with decreasing distance from the uppersemiconductor pattern USP. In some embodiments, the second thickness T2may decrease monotonically with decreasing distance from the uppersemiconductor pattern USP. The protrusion part PP may have a curvedsurface convexly directed toward the upper semiconductor pattern USP.

A maximum value of the second thickness T2 of the protrusion part PP maybe the same as or less than that of the first thickness T1 of the bodypart BP. A maximum thickness of the electrode EL may be the same as themaximum value of the first thickness T1 of the body part BP. Theelectrode EL may have a thickness that gradually decreases at theprotrusion part PP.

Between the first insulating layers IL1, the protrusion part PPprotruding toward the upper semiconductor pattern USP may be thinnerthan the body part BP (T2<T1). The second thickness T2 of the protrusionpart PP may gradually decrease with decreasing distance from the uppersemiconductor pattern USP. In some embodiments, the thickness T2 maydecrease monotonically with decreasing distance from the uppersemiconductor pattern USP. As a result, it may be possible to obtain arelatively large space, or a recess region RS which will be discussedbelow, between the protrusion parts PP vertically adjacent to eachother. The recess region RS may be stably or sufficiently filled withthe blocking insulating layer BK and the charge storage layer TL.

The first insulating layer IL1 may be recessed in a direction away fromthe upper semiconductor pattern USP, and, therefore, the recess regionRS may be defined. The recess region RS may be defined by the firstinsulating layer IL1 and a pair of vertically adjacent protrusion partsPP. Between the protrusion parts PP, the recess region RS may sinktoward a direction away from the upper semiconductor pattern USP.

The vertical insulating layer VP may include a data storage part DSP onthe protrusion part PP of the electrode EL and also include a connectionpart CNP on the first insulating layer IL1. The data storage part DSPmay be a portion of the cell region CR described above. The connectionpart CNP may include the cell separation region SCR described above. Theconnection part CNP may at least partially fill the recess region RS.The connection part CNP may be interposed between a pair of data storageparts DSP vertically adjacent to each other. For example, the connectionpart CNP may connect the pair of data storage parts DSP to each other.

The data storage part DSP may be interposed between the protrusion partPP of the electrode EL and the upper semiconductor pattern USP. The datastorage part DSP may be interposed between a tip end TI of theprotrusion part PP and the upper semiconductor pattern USP. The datastorage part DSP may include the blocking insulating layer BK, thecharge storage layer TL, and the tunnel insulating layer TN. The datastorage part DSP may not include the filling insulating layer FM. Forexample, the charge storage layer TL of the data storage part DSP maydirectly physically contact the tunnel insulating layer TN of the datastorage part DSP.

A NAND Flash memory device may be embodied as a three-dimensionalsemiconductor memory device according to some example embodiments ofinventive concepts. The data storage part DSP may be a region where dataare stored in the NAND Flash memory device. Data stored in the datastorage part DSP may be changed by Fouler-Nordheim tunneling induced bya difference in voltage between the electrode EL and the uppersemiconductor pattern USP.

The connection part CNP may include the blocking insulating layer BK,the charge storage layer TL, the filling insulating layer FM, and thetunnel insulating layer TN. The tunnel insulating layer TN of theconnection part CNP may be spaced apart from the charge storage layer TLacross the filling insulating layer FM. The filling insulating layer FMmay have a crooked or nonlinear surface CS conforming to a profile ofthe recess region RS. The filling insulating layer FM may have a flatsurface FS conforming to a profile of the upper semiconductor patternUSP. The tunnel insulating layer TN may contact the flat surface FS ofthe filling insulating layer FM, and, thus, extend linearly. The chargestorage layer TL may not contact the flat surface FS of the fillinginsulating layer FM. The charge storage layer TL may contact the crookedor nonlinear surface CS of the filling insulating layer FM. Therefore,differently from the tunnel insulating layer TN, the charge storagelayer TL may be crooked or have a nonlinear shape due to the fillinginsulating layer FM. Because the charge storage layer TL is formedcrookedly or with a nonlinear shape, as discussed below, the datastorage part DSP may be less likely to suffer loss of data storedtherein.

The connection part CNP may have a third thickness T3 vertically (e.g.,in the third direction D3) relative to the substrate 100. The thirdthickness T3 of the connection part CNP may gradually increase withdecreasing distance from the upper semiconductor pattern USP. In someembodiments, the third thickness may increase monotonically withdecreasing distance from the upper semiconductor pattern USP. Theconnection part CNP may have a thickness profile opposite to that of theprotrusion part PP discussed above.

The tunnel insulating layer TN of the connection part CNP may have afirst length L1. The charge storage layer TL of the connection part CNPmay have a second length L2. The second length L2 may be greater thanthe first length L1. The tunnel insulating layer TN of the connectionpart CNP may linearly extend from the data storage part DSP to anadjacent data storage part DSP, and, thus, the first length L1 may berelatively small. The charge storage layer TL of the connection part CNPmay be crooked or have a nonlinear shape while at least partiallyfilling the recess region RS, and, thus, the second length L2 may berelatively long. For example, the second length L2 may be about 1.5 to 5times the first length L1 in some embodiments.

A semiconductor memory device according to some example embodiments ofthe inventive concepts may be configured such that the length L2 of thecharge storage layer TL between neighboring data storage parts DSP maybe greater than a distance (e.g., L1) between the neighboring datastorage parts DSP. In this case, the data storage parts DSP may havetherebetween a relatively long path through which charges aretransferred.

Therefore, the semiconductor memory device according to some exampleembodiments of the inventive concepts may reduce or prevent data(charges) stored in the data storage part DSP from moving toward adifferent adjacent data storage part DSP. As a result, the semiconductormemory device according to some example embodiments of the inventiveconcepts may reduce or prevent loss of data stored in the data storagepart DSP and also improve in reliability.

FIGS. 6 to 11 illustrate cross-sectional views taken along line I-I′ ofFIG. 3, showing a method of fabricating a three-dimensionalsemiconductor memory device according to some example embodiments of theinventive concepts. FIGS. 12A and 12B illustrate enlargedcross-sectional views showing section M of FIG. 8. FIGS. 13A, 13B, and13C illustrate enlarged cross-sectional views showing section M of FIG.9. FIG. 14 illustrates an enlarged cross-sectional view showing sectionM of FIG. 11.

Referring to FIGS. 3 and 6, first insulating layers IL1 and sacrificiallayers HL may be vertically and alternately stacked on a portion of oran entire surface of a substrate 100 forming a stack structure ST. Asecond insulating layer IL2 may be formed on an uppermost sacrificiallayer HL. For example, the substrate 100 may be a silicon substrate, agermanium substrate, and/or a silicon-germanium substrate.

The first insulating layers IL1, the second insulating layer IL2, andthe sacrificial layers HL may be deposited by using thermal chemicalvapor deposition (CVD), plasma enhanced CVD, physical CVD process, oratomic layer deposition (ALD). The first insulating layers IL1 and thesecond insulating layer IL2 may be formed of a silicon oxide layer, andthe sacrificial layers HL may be formed of a silicon nitride layerand/or a silicon oxynitride layer.

Referring to FIGS. 3 and 7, channel holes CH may be formed to penetratethe stack structure ST and to expose the substrate 100. The channel holeCH may have a diameter that gradually decreases with decreasing distancefrom the substrate 100. In some embodiments, the diameter of the channelhole CH may monotonically decrease with decreasing distance from thesubstrate 100.

For example, the formation of the channel holes CH may include formingon the stack structure ST a mask pattern having openings that defineareas where the channel holes CH are formed, and performing an etchingprocess in which the mask pattern is used as an etching mask to etch thestack structure ST. Afterwards, the mask pattern may be removed. Thesubstrate 100 may be over-etched on its top surface during the etchingprocess. Accordingly, an upper portion of the substrate 100 may berecessed.

Referring to FIGS. 3 and 8, the first insulating layers IL1 exposed tothe channel holes CH may be partially etched to form recess regions RS.The sacrificial layers HL exposed to the channel holes CH may bepartially etched to form protrusion sections PPa. The procedure offorming the recess regions RS and the protrusion sections PPa will bedescribed in detail with reference to FIGS. 12A and 12B.

Referring to FIGS. 8 and 12A, an etching process may be performed toselectively etch the first insulating layers IL1 exposed to the channelholes CH. The etching process may include a wet etching process, whichuses an etching recipe capable of selectively etching the firstinsulating layers IL1 (and the second insulating layer IL2). Thesacrificial layers HL may not be etched during the etching process.

While the etching process is performed, the first insulating layers IL1may be recessed to form the recess regions RS. Each of the recessregions RS may be defined by a pair of vertically neighboringsacrificial layers HL and the first insulating layer IL1 therebetween.

Referring to FIGS. 8 and 12B, an etching process may be performed toselectively etch the sacrificial layers HL exposed to the channel holesCH. The etching process may include a wet etching process, which uses anetching recipe capable of selectively etching the sacrificial layers HL.The sacrificial layers HL may be partially etched. An etching depth ofthe sacrificial layers HL may be less than that of the first insulatinglayers IL1. Thus, each of the sacrificial layers HL may have theprotrusion section PPa that protrudes more toward a center of thechannel hole CH than the first insulating layer IL1.

Referring to FIGS. 3 and 9, vertical channel structures VS may be formedin corresponding channel holes CH. For example, lower semiconductorpatterns LSP may be formed on the substrate 100 exposed to the channelholes CH. The lower semiconductor patterns LSP may correspondingly filllower portions of the channel holes CH. The lower semiconductor patternsLSP may be formed by a selective epitaxial growth process in which thesubstrate 100 exposed to the channel holes CH is used as a seed layer.

A vertical insulating layer VP and an upper semiconductor pattern USPmay be formed to sequentially cover an inner sidewall of each of thechannel holes CH. Then, a buried insulating pattern VI may be formed topartially or completely fill the channel hole CH. A conductive pad PAmay be formed on an upper portion of each of the channel holes CH. Theprocedure of forming the vertical insulating layer VP, the uppersemiconductor pattern USP, and the buried insulating pattern VI will bedescribed in detail with reference to FIGS. 13A, 13B, and 13C.

Referring to FIGS. 9 and 13A, a blocking insulating layer BK may beconformally formed on the first insulating layer IL1 and the sacrificiallayer HL that are exposed to the channel hole CH. Thereafter, a chargestorage layer TL may be conformally formed on the blocking insulatinglayer BK. The blocking insulating layer BK and the charge storage layerTL may extend from the protrusion section PPa of the sacrificial layerHL toward the recess region RS. The blocking insulating layer BK and thecharge storage layer TL may be crookedly formed or formed to have anonlinear shape along profiles of the protrusion section PPa and therecess region RS.

For example, the blocking insulating layer BK may include a siliconoxide layer. The charge storage layer TL may include a silicon nitridelayer, a silicon oxynitride layer, or a silicon-rich nitride layer. Theblocking insulating layer BK and the charge storage layer TL may beformed by using atomic layer deposition (ALD) or chemical vapordeposition (CVD).

Referring to FIGS. 9 and 13B, a filling insulating layer FM may beformed to at least partially fill the recess region RS. The formation ofthe filling insulating layer FM may include forming an insulating layeron the charge storage layer TL exposed to the channel hole CH andperforming an etch-back process on the insulating layer. The etch-backprocess may be performed until a surface of the charge storage layer TLon the protrusion section PPa is exposed. For example, the fillinginsulating layer FM may include a silicon oxide layer, a silicon nitridelayer, and/or a silicon oxynitride layer.

Referring to FIGS. 9 and 13C, a tunnel insulating layer TN may beconformally formed on the charge storage layer TL and the fillinginsulating layer FM, which are exposed to the channel hole CH. Afterthat, an upper semiconductor pattern USP may be conformally formed onthe tunnel insulating layer TN. A buried insulating pattern VI may beformed on the upper semiconductor pattern USP, partially or completelyfilling the channel hole CH. A vertical insulating layer VP may comprisethe blocking insulating layer BK, the charge storage layer TL, thefilling insulating layer FM, and the tunnel insulating layer TN.

The vertical insulating layer VP may include a data storage part DSP onthe protrusion section PPa and a connection part CNP at least partiallyfilling the recess region RS. The filling insulating layer FM may beexcluded from the data storage part DSP.

The tunnel insulating layer TN and the upper semiconductor pattern USPmay be formed generally flat. Differently from the blocking insulatinglayer BK and the charge storage layer TL, the tunnel insulating layer TNand the upper semiconductor pattern USP may not be crooked or havenonlinear shapes.

The tunnel insulating layer TN may include, for example, either asilicon oxide layer or a high-k insulating layer, such as an aluminumoxide layer and a hafnium oxide layer. The upper semiconductor patternUSP may include silicon (Si), germanium (Ge), or a mixture thereof. Thetunnel insulating layer TN and the upper semiconductor pattern USP maybe formed by using atomic layer deposition (ALD) or chemical vapordeposition (CVD).

Referring to FIGS. 3 and 10, a separation insulating pattern SEP may beformed in an upper portion of the stack structure ST. The separationinsulating pattern SEP may be formed to extend in a second direction D2.For example, the formation of the separation insulating pattern SEP mayinclude etching the second insulating layer IL2 and an uppermostsacrificial layer HL to form a recess and filling the recess with aninsulating layer.

A third insulating layer IL3 may be formed on the stack structure ST.The third insulating layer IL3 may at least partially cover theconductive pads PA and the separation insulating pattern SEP. The thirdinsulating layer IL3 and the stack structure ST may be patterned to formtrenches TR penetrating the stack structure ST. The trenches TR maypartially expose the substrate 100. The trenches TR may extend in thesecond direction D2 along the stack structure ST.

Referring to FIGS. 3 and 11, the sacrificial layers HL may becorrespondingly replaced with electrodes EL. The substrate 100 exposedto the trenches TR may be doped with impurities to form common sourceregions CSR. An insulating spacer SP and a common source plug CSP may beformed to sequentially fill each of the trenches TR. The common sourceplug CSP may be coupled to the common source region CSR. The procedureof forming the electrodes EL will be described in detail with referenceto FIGS. 14 and 5A.

Referring to FIGS. 11 and 14, the sacrificial layers HL exposed to thetrenches TR may be selectively removed to form empty spaces ES. Theselective removal of the sacrificial layers HL may include performing awet etching process that uses an etching recipe capable of selectivelyetching the sacrificial layers HL except for the first insulating layersIL1 and the blocking insulating layer BK.

Referring to FIGS. 11 and 5A, a dielectric pattern GI, a barrier patternBM, and an electrode pattern GM may be sequentially formed in each ofthe empty spaces ES. The dielectric pattern GI may be conformally formedto directly cover the first insulating layer IL1 and the blockinginsulating layer BK. The barrier pattern BM may be conformally formed todirectly cover at least a portion of the dielectric pattern GI. Theelectrode pattern GM may be formed to partially or completely fill theempty space ES. An electrode EL may comprise the dielectric pattern GI,the barrier pattern BM, and the electrode pattern GM, which are formedin each of the empty spaces ES.

The dielectric pattern GI may include, for example, a silicon oxidelayer, a silicon nitride layer, a silicon oxynitride layer, and/or ahigh-k dielectric material. The barrier pattern BM may includeconductive metal nitride. The electrode pattern GM may include aconductive material selected from the group consisting of dopedsemiconductors, metals, and transition metals.

Referring back to FIGS. 3 and 4, a fourth insulating layer IL4 may beformed on the third insulating layer IL3. Bit line contact plugs BPLGmay be formed to penetrate the third and fourth insulating layers IL3and IL4 and to make connections with corresponding vertical channelstructures VS. Bit lines BL may be formed on the fourth insulating layerIL4 and may be coupled to the bit line contact plugs BPLG.

In a fabrication method according to some example embodiments of theinventive concepts, as shown in FIGS. 12A and 12B, the first insulatinglayer IL1 and the sacrificial layer HL may be partially etched to formthe recess region RS before the formation of the charge storage layerTL. The charge storage layer TL may be crookedly formed so as to have anonlinear shape by the recess region RS. As shown in FIG. 13C, a lengthL2 of the charge storage layer TL between neighboring data storage partsDSP may be greater than a distance (e.g., L1) between the neighboringdata storage parts DSP. The data storage parts DSP may have therebetweena relatively long path through which charges are transferred, and, as aresult, the data storage part DSP may be less likely to suffer from lossof data stored therein and devices formed in accordance with someembodiments of the inventive concept may have improved reliability.

The fabrication method according to some example embodiments of theinventive concepts may reduce or prevent loss of data stored in the datastorage part DSP without performing a complicated pattering process thatremoves the charge storage layer TL between the data storage parts DSP.As a result, it may be possible to simplify methods of fabricatingsemiconductor devices and to reduce costs for fabricating semiconductordevices.

FIGS. 15 to 22 illustrate enlarged cross-sectional views of section Mdepicted in FIG. 4, showing a three-dimensional semiconductor memorydevice according to some example embodiments of the inventive concepts.In the description of embodiments that follows, a detailed descriptionof technical features repetitive to those described above with referenceto FIGS. 3, 4, 5A, and 5B will be omitted, and differences thereof willbe discussed in detail.

As one example of the inventive concepts, referring to FIGS. 3, 4, and15, air gaps AG may be provided in the filling insulating layer FM. Forexample, the air gap AG may be defined in the filling insulating layerFM of the connection part CNP. The air gap AG may be at least partiallysurrounded by the filling insulating layer FM and the tunnel insulatinglayer TN. The filling insulating layer FM may separate the air gap AGfrom the charge insulating layer TL. The tunnel insulating layer TN mayseparate the air gap AG from the upper semiconductor pattern USP.

Referring again to FIGS. 9 and 13B described above, the fillinginsulating layer FM may not completely fill the recess region RS.Subsequently, as shown in FIGS. 9 and 13C, the tunnel insulating layerTN may be formed on the filling insulating layer FM, which may result inthe formation of the air gap AG at least partially surrounded by thefilling insulating layer FM and the tunnel insulating layer TN.

As one example of the inventive concepts, referring to FIGS. 3, 4, and16, the blocking insulating layer BK, the charge storage layer TL, andthe tunnel insulating layer TN of the vertical insulating layer VP maybe sequentially stacked on the electrode EL. The tunnel insulating layerTN may be crooked or have a nonlinear shape like the charge storagelayer TL. The filling insulating layer FM may be interposed between thetunnel insulating layer TN and the upper semiconductor pattern USP. Thetunnel insulating layer TN of the connection part CNP may be spacedapart from the upper semiconductor pattern USP across from the fillinginsulating layer FM.

As one example of the inventive concepts, referring to FIGS. 3, 4, and17, the vertical insulating layer VP may include the blocking insulatinglayer BK, the charge storage layer TL, and the tunnel insulating layerTN. Differently from the vertical insulating layer VP shown in FIGS. 5Aand 5B, the vertical insulating layer VP may not include the fillinginsulating layer FM. The blocking insulating layer BK, the chargestorage layer TL, the tunnel insulating layer TN, and the uppersemiconductor pattern USP may be sequentially stacked on the electrodeEL. The tunnel insulating layer TN may be crooked or have a nonlinearshape like the charge storage layer TL. The upper semiconductor patternUSP may be crooked or have a nonlinear shape like the charge storagelayer TL.

As one example of the inventive concepts, referring to FIGS. 3, 4, and18, the recess region RS may be recessed deeper than the recess regionRS shown in FIGS. 5A and 5B. For example, compared to a boundary betweenthe body and protrusion parts BP and PP of the electrode EL, the firstinsulating layer IL1 may be recessed in a direction away from the uppersemiconductor pattern USP. The first insulating layer IL1 may have asidewall at least partially covered with the blocking insulating layerBK, and the sidewall may be offset from the boundary between the bodypart BP and the protrusion part PP toward a direction away from theupper semiconductor pattern USP.

Because the recess region RS is more deeply recessed, the charge storagelayer TL may be more sharply crooked or may have deeper irregularities.The charge storage layer TL of the connection part CNP may have a lengthgreater than the length L2 of the charge storage layer TL of theconnection part CNP shown in FIGS. 5A and 5B. Therefore, the datastorage part DSP may be less likely to suffer from loss of data storedtherein.

Referring back to FIGS. 8 and 12B described above, after the sacrificiallayer HL is partially etched to form the protrusion section PPa, thefirst insulating layer IL1 may be selectively etched once more. Becausethe first insulating layer IL1 is etched once more, the recess region RSmay become even deeper. The re-etching of the first insulating layersIL1 may be the same as the etching process performed on the firstinsulating layers IL1 described with reference to FIGS. 8 and 12A.

As one example of the inventive concepts, referring to FIGS. 3, 4, and19, the air gap AG may be defined between the filling insulating layerFM and the charge storage layer TL of the connection part CNP. The airgap AG may be at least partially surrounded by the charge storage layerTL and the filling insulating layer FM. The air gap AG may be formedwhen the charge storage layer TL does not completely fill the recessregion RS.

As one example of the inventive concepts, referring to FIGS. 3, 4, and20, the air gap AG may be defined in the charge storage layer TL of theconnection part CNP. The air gap AG may be at least partially surroundedby the charge storage layer TL. The charge storage layer TL may includea bridge region BR interposed between the air gap AG and the fillinginsulating layer FM. The bridge region BR may separate the air gap AGfrom the filling insulating layer FM. The bridge region BR may be formeddue to overhang, which may occur when the charge storage layer TL isdeposited, and, accordingly, the air gap AG may be defined in the chargestorage layer TL.

As one example of the inventive concepts, referring to FIGS. 3, 4, and21, a first air gap AG1 may be defined in the charge storage layer TL ofthe connection part CNP. A second air gap AG2 may be defined in thefilling insulating layer FM of the connection part CNP. The first airgap AG1 may be substantially the same as the air gap AG described abovewith reference to FIG. 20, and the second air gap AG2 may besubstantially the same as the air gap AG described above with referenceto FIG. 15.

The first air gap AG1 and the second air gap AG2 may be defined in asingle connection part CNP. The first air gap AG1 and the second air gapAG2 may be located at substantially the same level relative to thesubstrate 100. The first air gap AG1 and the second air gap AG2 may behorizontally spaced apart from each other as shown in FIG. 21. In FIG.21, the second air gap AG2 is illustrated to have a size greater thanthat of the first air gap AG1, but embodiments of the inventive conceptsare not limited thereto. The size of the second air gap AG2 may be thesame as or less than that of the first air gap AG1.

As one example of embodiments of the inventive concepts, referring toFIGS. 3, 4, and 22, the charge storage layer TL may have the same shapeas that of the charge storage layer TL of FIG. 20, but may not includethe air gap AG therein. For example, the charge storage layer TL maycompletely fill the recess region RS.

FIG. 23 illustrates an enlarged cross-sectional view of section Ndepicted in FIG. 4, showing a three-dimensional semiconductor memorydevice according to some example embodiments of the inventive concepts.In the embodiment that follows, a detailed description of technicalfeatures repetitive to those discussed with reference to FIGS. 3 to 5Band 15 to 22 will be omitted, and differences thereof will be discussedin detail.

Referring to FIGS. 3, 4, and 23, the electrodes EL of the stackstructure ST may include a first electrode EL1, a second electrode EL2,a third electrode EL3, and a fourth electrode EL4 that are sequentiallystacked.

The first insulating layers IL1 may have different thicknesses from eachother. The first insulating layer IL1 between the first and secondelectrodes EL1 and EL2 may have a thickness greater than that of thefirst insulating layer IL1 between the second and third electrodes EL2and EL3. For example, a third distance L3 between the first and secondelectrodes EL1 and EL2 may be greater than a fourth distance L4 betweenthe second and third electrodes EL2 and EL3. The thickness of the firstinsulating layer IL1 between the second and third electrodes EL2 and EL3may be greater than that of the first insulating layer IL1 between thethird and fourth electrodes EL3 and EL4. For example, the fourthdistance L4 between the second and third electrodes EL2 and EL3 may begreater than a fifth distance L5 between the third and fourth electrodesEL3 and EL4.

Because the first and second electrodes EL1 and EL2 are spaced apart atthe third distance L3, which is relatively large, the charge storagelayer TL may not completely fill the recess region RS between the firstand second electrodes EL1 and EL2. Therefore, similar to the embodimentshown in FIG. 19, the air gap AG may be included in the verticalinsulating layer VP between the first and second electrodes EL1 and EL2.The air gap AG may be defined between the charge storage layer TL andthe filling insulating layer FM.

Similar to the embodiment shown in FIG. 20, the air gap AG may bedefined in the charge storage layer TL between the second and thirdelectrodes EL2 and EL3. Because the fourth distance L4 between thesecond and third electrodes EL2 and EL3 is less than the third distanceL3, the bridge region BR may be formed, which defines the air gap AG inthe charge storage layer TL between the second and third electrodes EL2and EL3. In this case, the charge storage layer TL between the secondand third electrodes EL2 and EL3 may include the bridge region BRinterposed between the air gap AG and the filling insulating layer FM.For example, the air gap AG between the first and second electrodes EL1and EL2 may have a size greater than that of the air gap AG between thesecond and third electrodes EL2 and EL3.

Because the fifth distance L5 between the third and fourth electrodesEL3 and EL4 is less than the fourth distance L4, the charge storagelayer TL may completely fill the recess region RS between the third andfourth electrodes EL3 and EL4. Therefore, similar to the embodimentshown in FIG. 22, the air gap AG may not be included in the chargestorage layer TL between the third and fourth electrodes EL3 and EL4.

In a semiconductor memory device according to some example embodimentsof the inventive concepts, a single cell array may include at least oneof a plurality of embodiments discussed above with reference to FIGS. 18to 22. For example, the charge storage layer TL according to theembodiment shown in FIG. 19 may be disposed between the first and secondelectrodes EL1 and EL2 of a cell array, the charge storage layer TLaccording to the embodiment shown in FIG. 20 may be placed between thesecond and third electrodes EL2 and EL3 of the cell array, and thecharge storage layer TL according to the embodiment shown in FIG. 22 maybe positioned between the third and fourth electrodes EL3 and EL4 of thecell array.

According to some example embodiments of the inventive concepts, asemiconductor memory device may reduce or prevent data (charges) storedin a certain data storage part from moving toward a different datastorage part adjacent to the certain data storage part. As a result, thesemiconductor memory device may reduce or prevent loss of data stored inthe data storage part and also provide improved reliability.

Although the present invention has been described in connection withsome example embodiments of inventive concepts illustrated in theaccompanying drawings, it will be understood to those skilled in the artthat various changes and modifications may be made without departingfrom the technical spirit and essential feature of inventive concepts.It will be apparent to those skilled in the art that varioussubstitution, modifications, and changes may be thereto withoutdeparting from the scope and spirit of inventive concepts.

What is claimed is:
 1. A semiconductor memory device, comprising: astack structure comprising a plurality of electrodes and a plurality ofinsulating layers that are alternately stacked on a substrate; and avertical channel structure penetrating the stack structure, wherein thevertical channel structure comprises a semiconductor pattern and avertical insulating layer between the semiconductor pattern and theplurality of electrodes, and wherein the vertical insulating layercomprises a charge storage layer, a filling insulating layer, and atunnel insulating layer, wherein the vertical insulating layer has acell region between the semiconductor pattern and each of the pluralityof electrodes, and a cell separation region between the semiconductorpattern and each of the plurality of insulating layers, wherein thecharge storage layer comprises a first portion and a remaining portionin the cell region, the first portion of the charge storage layer of thecell region is in physical contact with the tunnel insulating layer,wherein the filling insulating layer is between the semiconductorpattern and the remaining portion of the charge storage layer of thecell region, and wherein the filling insulating layer of the cell regionoverlaps a corresponding one of the plurality of electrodes in a firstdirection parallel to the substrate.
 2. The semiconductor memory deviceof claim 1, wherein a bottom surface of the cell region and a bottomsurface of the electrode adjacent to the cell region are atsubstantially same levels, respectively, and a top surface of the cellregion and a top surface of the electrode adjacent to the cell regionare at substantially same levels, respectively.
 3. The semiconductormemory device of claim 1, wherein the remaining portion of the chargestorage layer of the cell region is spaced apart from the tunnelinsulating layer across the filling insulating layer.
 4. Thesemiconductor memory device of claim 1, wherein the tunnel insulatinglayer is between the charge storage layer and the semiconductor pattern.5. The semiconductor memory device of claim 1, wherein the fillinginsulating layer of the cell separation region is between the chargestorage layer and the tunnel insulating layer.
 6. The semiconductormemory device of claim 1, wherein each of the plurality of electrodesincludes a protrusion part, which protrudes closer to the semiconductorpattern than an outer sidewall of the charge storage layer of the cellseparation region.
 7. The semiconductor memory device of claim 6,wherein the protrusion part has a curved surface.
 8. The semiconductormemory device of claim 6, wherein a maximum thickness of each of theplurality of protrusion parts is less than a maximum thickness of eachof the plurality of electrodes, respectively.
 9. The semiconductormemory device of claim 1, wherein the filling insulating layer of thecell region has a first thickness in a first direction, and the fillinginsulating layer of the cell separation region has the second thicknessin the first direction, the second thickness being greater than thefirst thickness.
 10. The semiconductor memory device of claim 1, whereinthe charge storage layer has a nonlinear shape between a pair of theplurality of electrodes adjacent to each other in a direction normal tothe substrate.
 11. A semiconductor memory device, comprising: a stackstructure comprising a plurality of electrodes and a plurality ofinsulating layers that are alternately stacked on a substrate; and avertical channel structure penetrating the stack structure, wherein thevertical channel structure comprises a semiconductor pattern and avertical insulating layer between the semiconductor pattern and theplurality of electrodes, and wherein the vertical insulating layercomprises a charge storage layer, a filling insulating layer, and atunnel insulating layer, wherein the filling insulating layer and thetunnel insulating layer are between the charge storage layer and thesemiconductor pattern, wherein the vertical insulating layer has a cellregion between the semiconductor pattern and each of the plurality ofelectrodes and a cell separation region between the semiconductorpattern and each of the plurality of insulating layers, wherein thefilling insulating layer of the cell region has a first thickness in afirst direction parallel to the substrate, wherein the fillinginsulating layer of the cell separation region has a second thickness inthe first direction, the second thickness being greater than the firstthickness, and wherein the filling insulating layer of the cell regionoverlaps a corresponding one of the plurality of electrodes in the firstdirection.
 12. The semiconductor memory device of claim 11, wherein abottom surface of the cell region and a bottom surface of the electrodeadjacent to the cell region are at substantially same levels,respectively, and a top surface of the cell region and a top surface ofthe electrode adjacent to the cell region are at substantially samelevels, respectively.
 13. The semiconductor memory device of claim 11,wherein the charge storage layer comprises a first portion and aremaining portion in the cell region; wherein the first portion of thecharge storage layer of the cell region is in physical contact with thetunnel insulating layer, and wherein the remaining portion of the chargestorage layer of the cell region is spaced apart from the tunnelinsulating layer across the filling insulating layer.
 14. Thesemiconductor memory device of claim 11, wherein the filling insulatinglayer of the cell separation region is between the charge storage layerand the tunnel insulating layer.
 15. The semiconductor memory device ofclaim 11, wherein the charge storage layer has a nonlinear shape betweena pair of the plurality of electrodes adjacent to each other in adirection normal to the substrate.
 16. A semiconductor memory device,comprising: a stack structure comprising a plurality of electrodes and aplurality of insulating layers that are alternately stacked on asubstrate; and a vertical channel structure penetrating the stackstructure, wherein the vertical channel structure comprises asemiconductor pattern and a vertical insulating layer between thesemiconductor pattern and the plurality of electrodes, and wherein thevertical insulating layer comprises a charge storage layer, a fillinginsulating layer, and a tunnel insulating layer, wherein the verticalinsulating layer has a cell region between the semiconductor pattern andeach of the plurality of electrodes and a cell separation region betweenthe semiconductor pattern and each of the plurality of insulatinglayers, wherein a bottom surface of the cell separation region and abottom surface of the insulating layer adjacent to the cell separationregion are at substantially same levels, respectively, wherein a topsurface of the cell separation region and a top surface of theinsulating layer adjacent to the cell separation region are atsubstantially same levels, respectively, wherein the filling insulatinglayer of the cell separation region extends from the bottom surface ofthe cell separation region to the top surface of the cell separationregion, and wherein the filling insulating layer of the cell regionoverlaps a corresponding one of the plurality of electrodes in a firstdirection parallel to the substrate.
 17. The semiconductor memory deviceof claim 16, wherein the cell region comprises a first cell region and asecond cell region adjacent to the first cell region in a directionnormal to the substrate, the cell separation region is between the firstand second cell regions, and the filling insulating layer extends fromthe first cell region toward the second cell region.
 18. Thesemiconductor memory device of claim 17, wherein the charge storagelayer comprises a first portion and a remaining portion in the firstcell region; wherein the first portion of the charge storage layer ofthe first cell region is in physical contact with the tunnel insulatinglayer, and wherein the filling insulating layer is between thesemiconductor pattern and the remaining portion of the charge storagelayer of the first cell region.
 19. The semiconductor memory device ofclaim 16, wherein the filling insulating layer of the cell separationregion is between the charge storage layer and the tunnel insulatinglayer.
 20. The semiconductor memory device of claim 16, wherein thecharge storage layer has a nonlinear shape between a pair of theplurality of electrodes adjacent to each other in a direction normal tothe substrate.